Technical Field
The present invention relates to generally observing network activity. More particularly, the present invention relates to integrating a port within a network system to passively observe the network or inject test traffic into a network port. More particularly, the present invention relates to a spacecraft integrated system allowing a user to observe the spacecraft network at a port on a box without effecting network operation or inject test traffic into a network port.
Background Information
Spacecraft are highly technical machines that include highly complicated and detailed electrical networks. The electrical networks control many aspects of spacecraft function, such as communication, environmental homeostasis, and power. Often times the physical circuits and electrical wiring defining these networks are housed in boxes on the spacecraft.
Payloads and other spacecraft subsystems are becoming increasingly more complex and adding extensive high speed networking capabilities. Similarly, satellites and spacecraft themselves are becoming more complex with high speed networks connecting subsystems such as sensors, payloads, processing boxes, communications systems and spacecraft control systems. Many of these networks extend from individual integrated circuits, circuit cards, electronics boxes, and subsystems across the full satellite system and use packet-based communication standards such as RapidIO or Gigabit Ethernet. These communication standards and networks are often based on high speed serializer/deserializer (SERDES) physical layer signaling protocols. Due to spacecraft manufacturing standards and requirements to minimize weight, manage heat dissipation and ensure high reliability, it is extremely time consuming and expensive to open spacecraft boxes or disassemble parts of a spacecraft under construction to investigate an anomaly. The spacecraft integration and test can take more than one year to complete.
Prior art network test systems exist and touch upon observing a network under test. An exemplary prior art network test system depicted in PRIOR ART FIG. 1 which displays a packet switched network that is coupled with network test equipment and the packet switched network traffic flows to the test equipment via the networks native packet switched protocol. A Serializer/Deserializer (SERDES) physical layer communications link using packet switched protocol (Gigabit Ethernet, RapidIO etc.) couples a device with SERDES ports to the packet switched network. The device(s) could be individual integrated circuits, circuit cards or boxes full of circuit cards. Packet switches can reside in multiple boxes and/or in a central packet switch box.
Further, the prior art network test system depicted in PRIOR ART FIG. 1 may include a SERDES receiver and a SERDES transmitter depicted in PRIOR ART FIG. 2. The prior art SERDES receiver includes a receiver/amplifier unit and a clock and data recovery unit. Receiver/Amplifier unit may incorporate equalization in the analog domain producing an analog output or equalization may be partly in the digital domain with feedback from clock and data recovery block. High speed data signal between the receiver/amplifier unit and the clock and data recovery unit may be analog or digital. Similarly, prior art SERDES transmitter includes a data serialization and clock combining unit and a de-emphasis and off-chip driver unit. High speed data signal between the data serialization and clock combining unit and the de-emphasis and off-chip driver unit may be analog or digital.
The prior art network depicted in PRIOR ART FIG. 1 may include various devices as depicted in PRIOR ART FIG. 3. Such devices may include an integrated circuit, a circuit board with components installed, or a box of electronics. If the electronic device function shown in PRIOR ART FIG. 3 is the network packet routing and queuing function, the portion of PRIOR ART FIG. 3 shown in the dashed lines may be a packet switch. A packet switch is one standard function within the network where inserting the test ports is convenient. Prior art systems use dedicated test input ports into SERDES receiver(s) (SERDES Rx) and dedicate test output ports from SERDES transmitter(s) (SERDES Tx) to interface with the test equipment.
In the prior art, packet switches are frequently used in the networks and represent convenient, standard components where the test ports could be inserted into the system. The prior art method of routing copied operational network traffic to a test port required modifying packet routing tables and changes the load on packet queues and operational network. Additionally, the routing of test traffic from external network test equipment through SERDES Rx, the packet routing function and into an operational network traffic output (SERDES Tx) port also requires modifying packet routing tables and changes the load on packet queues and operational network. These two scenarios modify the network behavior (congestion, latency, and throughput) which may hide anomalies or create new (false) anomalies and complicate system test and debug.
As depicted in PRIOR ART FIG. 4, a schematic view of design 600 is provided with a system-on-chip microprocessor including a real time test and debug port 602 using SERDES physical layer signaling, system-on-chip port 602. Port 602 is a traditional microprocessor test and debug port with a function that allows an operator to set watch points and do tracing of activity within the processor chip. The activity is then output through an Aurora protocol block 604. Microprocessor 600 is designed to provide software testing and maintenance observability and control through a high speed serial link on the SERDES. FIG. 4 further provides an example of a microprocessor that would be in a spacecraft or a commercial system. Multiple processors, such as 600, or other ASICs would have test ports at a component edge, a card edge, a box edge, or a spacecraft edge in order to be able to observe them or to send control or test signals back in. More particularly, FIG. 4 depicts a Freescale P5020 as 600. The Aurora protocol based test and debug port 602 is used for testing and debugging software running on the microprocessor—setting watch points and breakpoints in the code, tracing code execution at high speeds, etc. In this example there is no direct capability to monitor the network traffic going on and off chip using the prior art test and debug port 602. The main operational network ports of a conventional Freescale P5020 do not have any special real-time test and debug capability. Test port 602 for software debugging illustrates another type of SERDES test port that can be routed to the system test port. The Aurora protocol used for the test and debug port shown as 602 does not support packet switching as there is no routing information in the protocol.